To realize higher density recording of semiconductor memory apparatuses, development related to error correcting codes on digital data is underway. Error correcting codes can be roughly divided into an algebra-based error correction scheme and an error correction scheme through probability-based iterative calculations. Low density parity check codes (hereinafter referred to as “LDPC codes”) that belong to the latter are reported to exhibit excellent near Shannon limit performance.
LDPC coded data can be subjected to parallel processing with a relatively small circuit scale using a sum-product algorithm or the like. However, for LDPC coded data having a long code, full parallel processing in which all processing is performed in parallel requires many operation circuits to be all mounted, which is not realistic.
For this reason, a decoding apparatus is disclosed which uses a check matrix in a configuration with an array of square matrices to perform partial parallel processing in block units using each square matrix as one block.